Phase-locked-loop with reduced clock jitter

ABSTRACT

The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are divided by a predetermined rate to thereby reduce the frequency at a phase detection means ( 1 ) of the PLL circuit. The dividing step is inhibited in response to a detection of a phase-locked-state of the PLL circuit. Thus, after phase-lock has been achieved, extra reference dividers ( 6 ) added to decrease the comparison frequency are removed from the loop to thereby enable increase in the loop bandwidths and decrease in the dividing ratio within the loop.

The present invention relates to a phase-locked-loop (PLL) circuit forgenerating an oscillation signal in synchronism with an input referencesignal, in particular to a PLL architecture incorporating a tri-statePhase-Frequency Detector (PFD).

A PLL is widely used as a generator for a reference frequency signalsuch as a clock signal in a micro processor and a local oscillationsignal in a communication system and the like.

Standard Integer-N PLL architectures often incorporate a tri-state PFDwhich provides the advantage of being able to perform frequencydiscrimination, generating little reference breakthrough as compared toother detectors, and being edge triggered, which makes the phasedetection performance independent of the duty cycle of the signals onthe detector inputs.

In M. Soyuer and R. Meyer, “Frequency Limitations of a ConventionalPhase-Frequency Detector”, IEEE Journal of Solid State Circuits vol. 25,pp. 1019-1022, August 1990, it is demonstrated that conventional PFDshave an upper limit for the reference frequency at which frequencydiscrimination is possible. This upper limit is directly linked to thereset time of the PFD by the following equation:f _(max)=1/(2ΔR),wherein ΔR is the reset time of the PFD, which corresponds to the timeneeded to reset internal flops and includes internal delays of logicgates and the propagation time inside the flip-flops.

Thus, during a start-up procedure of the PLL where phase lock has notyet been achieved, a frequency higher that f_(max) can lead to permanentfrequency lock at wrong operation frequencies.

If a reference clock higher than f_(max) is needed, there are basicallytwo solutions given for the loop to be able to perform frequencydiscrimination:

1. Decreasing the reset time of the PFD, thus increasing f_(max).However, this option is limited by the possibilities of the technologyin which the PLL will be implemented.

2. Increasing the period of the reference signal at the input of thePFD, i.e. decreasing the comparison frequency. This may easily beachieved by preceding the PFD with a frequency divider (the referencedivider) in order to divide the reference frequency down by a certainfactor M. It is noted, that, in this case, the dividing ratio of thefrequency divider inside the loop (the main divider) also needs to bemultiplied by the same factor M to maintain a certain output frequency.

The second solution is an alternative often used in practice. FIG. 1shows a principle block diagram of a PLL circuit in which the secondsolution is implemented. According to FIG. 1 the PLL includes a PFD 1, acharge pump circuit 2, a low-pass filter 3, a voltage controlledoscillator (VCO) 4 and a frequency divider 5. Furthermore, referencedividers 6 are provided at both inputs of the PFD 1 to thereby decreasethe compared frequencies derived from an input reference signal and afeedback signal looped back from the output terminal via the frequencydivider 5.

In operation, the PFD 1 supplies the charge pump circuit 2 with phasedifference signals based on a phase difference between the comparedsignals at the input of the PFD 1. The charge pump circuit 2 convertsthe phase difference signals into an error signal, which exhibits alevel change proportional to the phase difference between the comparedsignals. The error signal is then smoothed by the low-pass filter 3 togenerate a control signal supplied to the VCO 4. The VCO 4 generates anoutput clock having an oscillation frequency which is controlled basedon the voltage level of the control signal. The frequency divider 5generates a divided signal by dividing the output clock at apredetermined dividing ratio N, thereby supplying the output thereof tothe PFD 1. When the entire circuit has reached a steady or locked stateof operation, i.e. a synchronized state after the synchronizationtransfer period, the frequencies and phases of the input referencesignal and the divided signal looped back to the other input of the PFD1 coincide with each other. Accordingly, the output clock supplied fromthe VCO 4 corresponds to a signal obtained by multiplying the inputreference signal by the dividing ratio N.

The above mentioned synchronization transfer period corresponds to atransient period required for transferring the PLL into the locked statefor synchronization and is determined by a sum of a pull-in period,referred to as a frequency synchronization period, and a locked-inperiod, referred to as a phase synchronization period.

However, the PLL arrangement shown in FIG. 1 has the followingdisadvantages.

The increased dividing ratio achieved by the reference dividers 6 in theloop increases the phase noise contribution from the PFD 1, charge pumpcircuit 2 and frequency divider 5, 6 to the loop. Furthermore, due tothe fact that the maximum band width is more or less proportional to thecompared reference frequency, decreasing the reference frequency by afactor M means that the maximum loop bandwidth is scaled by the samefactor M. This means that the time it takes for the loop to settle, i.e.the synchronization transfer period or settling time, is increased.

As a further disadvantage, the smaller loop bandwidth may degrade theoutput signal due to jitter caused by the VCO 4 and the low-pass filter3. If the reference dividing ratio M equals two for example, the maximumloop bandwidth is two times lower than is allowed without the referencedividers 6. This means that the output jitter variance due to the phasenoise of the VCO 4 and the thermal noise of a loop filter resistorprovided in the low-pass filter 3 will be about twice as high as withoutthe dividers.

It is therefore an object of the present invention to provide a PLLcircuit and a method for controlling such a PLL circuit, by means ofwhich a reference clock higher than the maximum allowed frequency of thePFD can be used without introducing the above disadvantages.

This object is achieved by a PLL circuit as claimed in claim 1 and acontrol method as claimed in claim 8.

Accordingly, the extra dividers are only introduced to enable frequencydiscrimination of the phase detection means before the PLL has achievedphase-lock. Thereby, a simple solution is provided, which avoids thedrawbacks of the prior art. Due to the fact that the frequency dividingmeans are removed from the loop using the inhibiting means, an increasein the loop bandwidth and a decrease in the dividing ratio can beprovided after phase-lock has been reached. Then, the only function ofthe phase detection means is to maintain the phase-lock, without thenecessity for frequency discrimination. This means that the reset timeof the phase detection means is allowed to be somewhat higher than halfthe period time of the reference signal. Therefore, the maximumoperation frequency of a given phase detection means is extended withoutthe drawbacks of the known second solution.

A further advantage of removing the extra dividers after phase-lock hasbeen achieved is that the close-in phase noise power density drops by afactor M², while the increased loop-bandwidth results in a moreeffective suppression of the VCO and loop filter jitter.

Preferably, lock detecting means are provided for detecting thephase-locked state and for supplying an inhibition control signal to theinhibiting means.

Furthermore, the inhibiting means may comprise switching means foropening a connection between the frequency dividing means and the phasedetection means. In this case, the switching means may be arranged toclose respective by-pass connections for supplying the input referencesignal and the feedback signal directly to the phase detection means,when the connection between the frequency dividing means and the phasedetection means has been opened. The inhibition control signal maycomprise a first control signal for opening the connection and thesecond control signal for closing the by-pass connection. The switchingmeans may preferably be arranged to perform the switching in synchronismwith the dividing operation of the frequency dividing means.

Further advantageous developments can be derived from the dependentclaims.

In the following, the present invention will be described in greaterdetail on the basis of a preferred embodiment with reference to theaccompanying drawings in which:

FIG. 1 shows a schematic block diagram of a conventional PLLarchitecture with reference dividers;

FIG. 2 shows a schematic circuit diagram of a PFD used in the PLLcircuit according to the preferred embodiment;

FIG. 3 shows a PLL circuit according to the preferred embodiment;

FIG. 4 shows a signaling diagram indicating input and output signals ofthe PFD shown in FIG. 2; and

FIG. 5 shows a principal block diagram of a lock detection circuit usedin the PLL circuit according to the preferred embodiment.

The preferred embodiment will now be described on the basis of anInteger-N PLL architecture incorporating a tri-state PFD 1 as shown inFIG. 3.

According to FIG. 3, a switching arrangement is provided which comprisesswitches S1 and S4 for closing a by-pass connection arranged forby-passing the reference dividers 6 and switches S2 and S3 for openingor closing a connection between the reference dividers 6 and therespective input terminals A, F of the PFD 1. The switching operation ofthe switches S1 to S4 is controlled by a control signal LOCK and aninverted control signal LOCK generated by a lock detection circuit 7.Due to the fact that the control signals LOCK and LOCK are of oppositelogical states, the switches S1 and S4 are closed when switches S2 andS3 are opened and vice versa. Accordingly, the switching arrangement canbe controlled to inhibit the frequency dividing operation of thereference dividers 6 in response to the control signals LOCK and LOCKgenerated by the lock detection circuit 7.

The lock detection circuit 7 is connected to the output terminals up, dnof the PFD 1.

FIG. 2 shows a schematic circuit diagram of the PFD 1 which consists oftwo D-Flip-Flops 11, 12 for outputting the respective logical outputsignals up and dn, respectively. The input terminals D of theD-Flip-Flops 11, 12 are set to the high logical level “1”, and the inputterminals A and F of the PFD 1 are connected to the edge triggered clockinput terminals of the D-Flip-Flops 11, 12. A tri-state output stage 13is provided by an AND-gate having its input terminals connected to therespective output terminals up and dn of the PFD 1, and having itsoutput terminal connected to the reset terminals of both D-Flip-Flops11, 12. The circuit basically functions as an up-down counter where asignal at the input terminal A causes a signal or up-count at the outputterminal up corresponding to the respective D-Flip-Flop 11, and a signalat the other input terminal F of the PFD 1 causes a down-count at thecorresponding output terminal dn of the other D-Flip-Flop 12. Thus, whenthe frequencies at the input terminals A, F of the PFD 1 are equal butthe phase of the signal at the terminal A leads that of the signal atthe terminal F, the output signal of the D-Flip-Flop 11 corresponding tothe input terminal A is held “ON” or at the high logical level “1” for atime corresponding to the phase difference. When the phase of the signalat the input terminal A lags that of the signal at the input terminal F,the other output terminal dn is held “ON” or at the high logical level.

When the frequency of one of the input terminals A, F of the PFD 1 ishigher than that of the other, the respective output terminal is held“ON” for most of the input signal cycle time, and for the remainder ofthe cycle both outputs up and dn are “OFF”, i.e. high impedance state.Subsequently, the output voltage at the low-pass filter 3 varies untilthe input signals of the PFD 1 are equal in both phase and frequency. Atthis stabile point, the voltage at the output of the low-pass filter 3remains constant.

FIG. 4 shows respective waveforms at the input terminals A, F and acorresponding output signal which combines the signals at the outputterminal up and dn to a single signal, wherein a positive pulseindicates a high logical level at the output terminal up and a negativepulse indicates a high logical level at the output terminal dn. As canbe gathered from FIG. 4, a positive pulse (pulse of the up-signal) isobtained when the phase of the signal at the terminal A precedes, whilea negative pulse (pulse of the dn-signal) is obtained, when the phase ofthe signal at the terminal F precedes.

The charge pump circuit 2 shown in FIG. 3 is arranged to generate anerror signal which may be a current pulse of a constant magnitude andwith a pulse width proportional to the phase error given by thedifference output signals at the terminals up and dn. Namely, the outputline of the charge pump circuit 2 is charged during a high level at theoutput terminals up and discharged during a high level at the outputterminals dn. Thus, the charge from circuit 2 converts the phasedifference output signals at the terminals up and dn into an errorsignal having a voltage level based on the phase difference between thecompared signals at the input terminals A and F of the PFD 1.

The low-pass filter 3 shown in FIG. 3 may comprise a resistor andcapacitor arrangement adapted to generate a control signal by smoothingthe error signal output from the charge pump circuit 2. The VCO 4 thengenerates an output clock having an oscillation frequency controlled bythe control signal. The frequency divider 5 divides the output clock ofthe VCO 4 to generate a feedback signal having a frequency equal to thatof the input reference signal supplied to the upper one of the referencedividers 6.

Furthermore, the lock detection circuit 7 is arranged to judge thesteady or lock state of the PLL by detecting a small phase error betweenthe compared input signals of PFD 1. To remain in the locked state, thePLL circuit requires some small adjustments. The variation is dependenton the loop parameters and back-lash time, typically in the order ofseveral ns. If the PLL circuit is in the locked state, only very smallpulses will be output at the output terminals up and dn of the PFD 1.

FIG. 5 shows a schematic block diagram of an exemplary implementation ofthe lock detection circuit 7. According to FIG. 5, the phase differenceoutput signals at the terminals up and dn are combined in a NOR gate 71arranged to produce a high level output signal if both input signals areat a logical low level “0”. If at least one of the input signalssupplied from the terminals up and dn of the PFD 1 is at a high level,the output of the NOR gate 71 will switch to the low level. Thus, in thelocked state, the output signal of the NOR gate 71 is mainly at a highlevel state and changes to a low level state during the short pulsesindicating the phase error. These pulses are filtered out by a lowpassed filter 72, i.e. an RC network or the like, and a Schmitt triggercircuit 73 produces a steady state level, wherein a high logical levelindicates the locked state and a pulsed output indicates an out-of-lockstate.

The output signal of the Schmitt trigger circuit 73 is supplied to thetrigger input of a monostable flip-flop 74 which generates the controlsignals LOCK and LOCK. During the locked state of the PLL, no outputpulses are generated at the Schmitt trigger circuit 73 and themonostable flip-flop 74 maintains a low level state at its non-invertedQ output and a high level state at its inverted Q output. Thus, the Qoutput can be used for generating the control signal LOCK. On the otherhand, in the out-of-lock state of the PLL circuit, pulses are generatedat the output of the Schmitt trigger circuit 73, which continuouslyretrigger the monostabile flip-flop 74 to maintain its Q output at ahigh state, provided that the inherent time period of the monostableflip-flop 74 is set to a value higher than the maximum pulse period ofthe output signal of the Schmitt trigger circuit 73. Thus, the Q outputof the monostabile flip-flop 74 can be used for generating the controlsignal LOCK.

Thus, a simple solution is introduced to avoid the initially mentioneddrawbacks of the conventional PLL circuit shown in FIG. 1. In summary,some time after phase (and frequency) lock has been achieved, the twoextra reference dividers 6 which were added to decrease the referencefrequency at the input of the PFD 1 are removed from the PLL loop usingthe switches S1 to S4, thereby enabling an increase in the loopbandwidth and decrease in the total dividing ratio. After phase-lock hasbeen reached, the only function of the PFD 1 is to maintain thephase-lock without the necessity for frequency discrimination. Thismeans that the reset time of the PFD 1 is allowed to be somewhat higherthan half a period of the reference signal. Therefore, the maximumoperation frequency of the PFD 1 can be extended without the drawbacksof the conventional PLL circuit shown in FIG. 1.

It is noted, that the removing or inhibiting of the extra referencedividers 6 “on-the-run” has to be performed in such a manner that phasedisturbances are prevented in the loop, as this might force the loop outof lock. This may be achieved by linking the timing of switches S1 to S4to the dividing states of the reference dividers 6, so that switchingcan be timed to occur just after the active edges of the output signalsof the reference dividers 6 reach the edge triggered input terminals Aand F of the PFD 1. Moreover, switching noise at the input terminals Aand F of the PFD 1 should be prevented by corresponding circuit designmatters.

The present invention is especially useful in systems where broadbandPLLs with very high reference frequencies are to be used, for instancein clock conversion circuits for optical networks. In such a scenario,the PFD 1 could be designed to discriminate frequencies at a referencefrequency of 625 MHz and could be used for “phase discrimination only”if operation at a reference frequency of 2.5 GHZ would be required.

It is noted that the present invention is not restricted to the specificcircuit described in connection with the above preferred embodiment. Anykind of lock detection circuit arranged for generating a control signalindicating a locked state of the PLL can be used. The lock detectioncircuit may even be replaced by a simple timer circuit which counts apredetermined time period, e.g. one second, after the start of asynchronization operation, and then activates the inhibiting means, e.g.the switches S1 to S4, to inhibit the frequency dividing operation ofthe reference dividers 6 after the predetermined time period haselapsed. The predetermined time period has to be set to a value largeenough to ensure that the PLL has reached the phase locked state. Anykind of inhibiting means could be implemented, which is suitable forinhibiting the function of the reference dividers 6 in response to thecontrol signal obtained from the lock detection circuit 7 or the timercircuit. Thus, the present invention may vary within the scope of theattached claims.

1. A phase-locked-loop circuit for generating an oscillation signal insynchronism with an input reference signal, said phase-locked-loopcircuit comprising: a) phase detecting means for detecting a phasedifference between a first signal derived from said input referencesignal and a second signal derived from said oscillation signal, and forgenerating a control signal corresponding to said phase difference; b)frequency control means for controlling the frequency of saidoscillation signal based on said control signal; c) frequency dividingmeans for dividing the frequency of said input reference signal by afactor M and dividing a feedback signal derived from said oscillationsignal by the same factor M to generate said first and second signal,respectively; and d) inhibiting means for inhibiting the operation ofsaid frequency dividing means, such that the frequency of said inputreference signal is no longer divided by the factor M, and the feedbacksignal derived from said oscillation signal is no longer divided by thesame factor M, when said phase-locked-loop circuit has reached aphase-locked state.
 2. A circuit according to claim 1, furthercomprising lock detection means for detecting said phase-locked stateand for supplying an inhibition control signal to said inhibiting means.3. A circuit according to claim 1, further comprising timer means forcounting a predetermined time period after the start of asynchronization operation, and for supplying an inhibition controlsignal to said inhibiting means when said predetermined time period haselapsed.
 4. A circuit according to claim 2, wherein said inhibitingmeans comprises switching means for opening a connection between saidfrequency dividing means and said phase detection means (1) in responseto said inhibition control signal.
 5. A circuit according to claim 4,wherein said switching means is arranged to close respective by-passconnections for supplying said input reference signal and said feedbacksignal directly to said phase detection means, when said connectionbetween said frequency dividing means and said phase detection means hasbeen opened.
 6. A circuit according to claim 5, wherein said inhibitioncontrol signal comprises a first control signal for opening saidconnection and a second control signal for closing said by-passconnections.
 7. A circuit according to claim 4, wherein said switchingmeans is arranged to perform said switching in synchronism with thedividing operation of said frequency dividing means.
 8. A circuitaccording to claim 1, wherein said phase detection means is a phase andfrequency detector.
 9. A method of controlling a phase-locked-loopcircuit, said method comprising the steps of: a) dividing the frequencyof an input reference signal of said phase-locked-loop circuit by afactor M and dividing a feedback signal derived from an oscillationsignal by the same factor M; b) supplying said divided input referencesignal and said divided feedback signal to a phase detection means ofsaid phase-locked-loop circuit; c) inhibiting said dividing step inresponse to a detection of a phase-locked state of saidphase-locked-loop circuit such that the frequency of said inputreference signal is no longer divided by the factor M, and the feedbacksignal derived from said oscillation signal is no longer divided by thesame factor M; and d) controlling the frequency of the oscillationsignal based on a control signal corresponding to a detection of a phasedifference between the input reference signal and the oscillationsignal.